In conventional delay line ADCs (as a non-limiting example of an ADC using cell-based detection in strings of consecutively coupled detection cells) a sampling window having a size (number of detection cells) conforming to the desired bit resolution of the delay line ADC is required. Consider, for example, a differential delay line ADC including, for each of its two delay lines, a total number of N detection units (detection cells, delay units, delay cells, unit cells) in the sampling window. This ADC would have to also include a corresponding number of sampling latches (e.g., including flip flops) together with an encoder (digital encoder, e.g., thermal to binary) capable of reading out the N values held by these N detection units and appropriately processing these N values. A single-ended delay line ADC with the same bit resolution would be required to include, for its measurement line, a total number of (2N−1) detection units in the sampling window and corresponding sampling latches together with an encoder capable of reading out the (2N−1) values held by these (2N−1) detection units and appropriately processing these (2N−1) values. Accordingly, complexity, wiring, footprint and current consumption of conventional delay line ADCs increase in proportion to their desired bit resolution.